Wrap-back test system and method

A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

We claim:

1. A wrap back test system for detection of intra-domain errors of an integrated I/O interface core of an integrated circuit, comprising in operative combination:

a) an integrated transmitter, said transmitter comprising:

i) a transmitter input stage for receiving transmitter input data, said input data encoded with an alignment pattern, said input data having a first format and said input data having a particular timing, and

ii) a transmitter converter stage for converting said input data into transmitter output data, said output data having a second format;

b) an integrated receiver, said receiver comprising:

i) a receiver converter stage for receiving said output data for conversion of said output data to said first format to provide received reconverted data,

ii) a receiver alignment stage for extracting said alignment pattern from said received reconverted data, and for aligning said received re converted data to conform to said particular timing of said input data,

c) a first switching circuit in electrical cooperation with said transmitter input stage having a first open condition, and a second closed condition, said second closed condition for shunting input test data to said receiver alignment stage to provide wrap back data to said receiver alignment stage, said first switching circuit second closed condition being enabled upon assertion of a wrap back signal to the I/O interface core;

d) a second switching circuit in electrical cooperation with said receiver alignment stage having a first open position to permit receipt of received reconverted data from said receiver converter stage, and a second closed condition for receiving said wrap back data for alignment of said wrap back data to provide output test data, and for halting receipt of said received reconverted data upon assertion of said wrap back signal to the I/O interface core; and

e) an error analysis circuit for comparing said output test data with said input test data.

2. A wrap back test system as in claim 1 wherein said I/O interface core is a serializer/deserializer interface for converting alignment coded parallel formatted data to serial formatted data for transmission, and for converting serial formatted data to parallel formatted data for reception.

3. A wrap back test system as in claim 2 further comprising an in-core built-in self-test (BIST) circuit for providing said input test data to said transmitter input stage, wherein said input test data is pseudo-random and alignment encoded.

4. A wrap back test system as in claim 1 wherein said first switching circuit includes semiconductor switching devices, said first switching circuit being designed to maintain the direct current balance of the I/O interface core.

5. A wrap back test system as in claim 4 wherein said semiconductor switching devices are MOSFET transistors.

6. A wrap back test system as in claim 1 wherein said second switching circuit includes semiconductor switching devices, said second switching circuit being designed to maintain the direct current balance of the I/O interface core.

7. A wrap back test system as in claim 6 wherein said semiconductor switching devices are MOSFET transistors.

8. A wrap back test system as in claim 1 wherein said error analysis circuit is disposed in an in-core built-in self-test (BIST) and includes an error counter and and error trace buffer for determining and reporting the bit-error rate of the output test data as compared to the input test data.

9. A wrap back test system for detection of intra-domain errors of an integrated I/O interface circuit core of an integrated circuit, comprising in operative combination:

a) means for transmitting data, said transmitting means comprising:

i) a transmitter input means for receiving input data, said input data encoded with an alignment pattern, said input data having a first format and said input data having particular timing, and

ii) a data conversion means for converting said input data from said first format into output data having a second format;

b) means for receiving transmitted data, said receiving means comprising:

i) a receiver conversion means for converting said transmitted output data from said second format to said first format to provide received reconverted data, and

ii) a receiver data alignment means for extracting said encoded alignment pattern from the reconverted data, and for aligning the reconverted data to conform to said input data timing;

c) a first data switching means for switching input test data from said transmitter input means to said receiver data alignment means upon assertion of a wrap back signal to the I/O interface circuit core, said input test data encoded with said alignment pattern;

d) a second switching means for receiving said input test data from said transmitter input means for decoding of said alignment pattern for alignment of said input test data to provide output test data, and for halting receipt of said received reconverted data upon assertion of said wrap back signal to the I/O interface circuit core; and

e) an error analysis means for comparing said output test data with said input test data.

10. A wrap back test system as in claim 9 wherein said I/O interface circuit core is a serializer/deserializer interface for converting alignment coded parallel formatted data to serial formatted data for transmission, and for converting serial formatted data to parallel formatted data for reception.

11. A wrap back test system as in claim 9 further comprising an in-core built-in self-test (BIST) means for providing said input test data to said transmitter input means, wherein said input test data is pseudo-random and alignment encoded.

12. A wrap back test system as in claim 9 wherein said first data switching means includes semiconductor switching devices, said first data switching means being designed to maintain the direct current balance of the I/O interface circuit core.

13. A wrap back test system as in claim 12 wherein said semiconductor switching devices are MOSFET transistors.

14. A wrap back test system as in claim 9 wherein said second data switching means includes semiconductor switching devices, said second data switching means being designed to maintain the direct current balance of the I/O interface circuit core.

15. A wrap back test system as in claim 14 wherein said semiconductor switching devices are MOSFET transistors.

16. A wrap back test system as in claim 9 wherein said error analysis means is disposed in a built-in self-test (BIST) means and includes an error counter and an error trace buffer for determining and reporting a bit-error rate of the output test data as compared to the input test data.

17. A wrap back test method for detection of intra-domain errors of an integrated I/O interface core of an integrated circuit, comprising the following steps:

a) providing said integrated I/O interface core having both a transmitter section and a receiver section, said transmitter section comprising:

i) a transmitter input stage for receiving transmitter input data, said input data encoded with an alignment pattern, said input data having a first format and said input data having a particular timing, and

ii) a transmitter converter stage for converting said input data into transmitter output data, said output data having a second format,

and said receiver section comprising:

iii) a receiver converter stage for receiving said transmitter output data for conversion of said output data to said first format to provide received reconverted data,

iv) a receiver alignment stage for decoding said alignment pattern from said received reconverted data, and for aligning said received reconverted data to conform to said transmitter input data timing,

said transmitter section further comprising:

v) a first switching circuit in electrical cooperation with said transmitter input stage having a first open condition, and a second closed condition, said second closed condition for shunting transmitter input test data to said receiver alignment stage to provide wrap back data to said receiver alignment stage, said first switching circuit second closed condition being enabled upon assertion of a wrap back signal to the I/O interface core, and

said receiver section further comprising:

vi) a second switching circuit in electrical cooperation with said receiver alignment stage having a first open position to permit receipt of received reconverted data from said receiver converter stage, and a second closed condition for receiving said wrap back data for alignment of said wrap back data to provide output test data, and for halting receipt of said received reconverted data, said second closed condition being enabled upon assertion of said wrap back signal to the I/O interface core, and

an error analysis circuit for comparing said output test data with said input test data.

b) asserting a wrap back test enable signal to the I/O interface core to enable said second closed condition of said first switching circuit, and to enable said second closed condition of said second switching circuit;

c) inputting test data into said transmitter input stage, said input test data encoded with said alignment pattern;

d) shunting said input test data directly to said receiver alignment stage to bypass said transmitter converter stage;

e) decoding said alignment pattern from said shunted input data for alignment of said input test data;

f) aligning said input test data to provide aligned output test data; and

g) comparing said aligned output test data with said input test data.

18. A wrap back test method as in claim 17 wherein said I/O interface core is a serializer/deserilizer I/O interface core.

19. A wrap back test method as in claim 17 wherein said step of asserting said wrap back test enable signal is initiated off-chip via a wrap back enable pin on the integrated circuit accessible off-chip.

20. A wrap back test method as in claim 17 wherein said comparing step is performed by an in-core built-in self-test (BIST) circuit, said BIST circuit includes an error counter and an error trace buffer for determining and reporting a bit-error rate of the output test data as compared to the input test data.