Kendall, Burton; King, Thomas;

System for processing information

A system is provided to receive and process information including a processor, an operator station and an interconnect processor. The interconnect processor is coupled to the processor by a first bus, and the interconnect processor is coupled to the operator station by a second bus.

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We claim:

1. A system for receiving and processing information comprising:

(a) a first bus and a second bus;

(b) a plurality of processors coupled to said first and second buses;

(c) interconnect processor means to receive information, process information and transmit information, said interconnect processor means including a microcomputer wherein said microcomputer is coupled to said first bus via a first path including a receiver/transmitter and said microcomputer is coupled to said second bus via a second path including a receiver/transmitter, and said first and second paths are separate from one another so that data can be transferred between said microcomputer and said first bus at the same time the data is being transferred between said microcomputer and said second bus; and

(d) operator station and computer means to receive information from an operator and to display information and coupled to said first bus to receive information from said processors.

2. A system according to claim 1 wherein said operator station means is coupled to said second bus to transmit and receive information via said second bus and said operator station is not directly coupled to said first bus.

3. A system according to claim 1 wherein said processors are continuous control processors.

4. A system according to claim 3 wherein said interconnect processor means is constructed and arranged to permit cascading of at least two continuous control processors.

5. A system according to claim 1 wherein said processors include at least one first continuous control processor coupled to receive information from said interconnect processor means via said first bus means.

6. A system according to claim 1 wherein said processors include an analog input processor.