Sundet, James W.;

Solid state storage device

A solid state storage device is disclosed. The storage sections of the device are divided into two groups, with each group including at least one, and as many as four storage sections. A port is provided for delivering words to and receiving words from the sections. A data path between the port and the device is two words wide, with one word received from or delivered to each group. Each section includes a word storage register, with the registers of different sections in the same group being connected in a series fashion to provide a one word data path between the storage sections. Words stored or retrieved from a section are passed through its respective register. In a write operation, words to be stored are transmitted serially from register to register and captured by all sections simultaneously on the same clock cycle. Addressing means within each section then routes the word to the appropriate memory circuit within the section. In a read operation each section loads its register simultaneously, after which the data words are transmitted in a serial fashion from register to register out of the memory to the port. The memory circuits within each section are organized into a plurality of banks, each of which may be addressed independently of one another, so that a section may capture at least one word per clock cycle. A further circuit is provided to reverse the order of words received from the port during a write operation to cause the words to be in proper order when read from the memory.

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What is claimed is:

1. A high capacity, high bandwidth solid state storage system comprising:

a plurlity of storage sections each including RAM organized into a plurality of addressable memory locations for storing data, said system configured to include up to a maximum of s storage sections, where s is an integer greater than one;

each of said storage sections including addressing means for referencing said memory locations in said RAM so that data may be read or written simultaneously in each of said sections;

each of said sections including a pipeline input register for holding a word of data to be stored in the section, each of said input pipeline registers connected to said RAM so that when said RAM is referenced by said addressing means the respective words of data in said input registers are written into the respective sections in the referenced memory locations simultanuously;

means for connecting all of said input registers to provide a one-word wide data input pipeline between said storage sections, said data input pipeline having an input for receiving words to be stored in said sections;

input port means for receiving data words from an input data bus and supplying said data words to said input of said data input pipeline in synchrony with a first high bandwidth clock signal; and

write control means connected to said input pipeline registers for,

(a) causing said input registers to synchronously pass data words from one to another along said data input pipeline from section to section away from said input port means at the rate of said first clock signal;

(b) causing said addressing means to reference said RAM every n clock periods of said first clock signal, where n is an integer equal to the maximum number s of said storage sections in a fully configured system, so that the data words in said input registers during said reference are captured and written into said storage sections, each of the individual storage sections storing the data word held in its corresponding input register whereby up to s words of data may be stored every n clock periods of said first clock signal; and

(c) causing said input port means to supply w words every n clock periods of said first clock signal, where w is an integer equal to the number of sections configured in said system, said w words supplied so that they are captured simultaneously in said sections during said reference;

each of said sections including a pipeline output register, each of said output registers for holding a data word and connected to said RAM so that when said RAM is referenced by said addressing means the words in the referenced memory locations are transferred into the respective output registers;

means for connecting all of said output registers to provide a one-word wide data output pipeline between said storage sections, said data output pipeline having an output for outputting words retrieved from said sections;

output port means for receiving data words from said data output pipeline and conveying the received words to an output data bus in synchrony with a second high bandwidth clock signal;

read control means connected to said output registers for,

(a) causing said output registers to synchronously pass data words from one to another along said data output pipeline from section to section towards said output port means at the rate of said second clock signal;

(b) causing said addressing means to reference said RAM every n clock periods of said second clock signal so that data is captured in said output registers simultaneously from said storage sections during said reference, each of the individual storage sections providing a data word to its corresponding output register whereby up to s words of data may be read every n clock periods of said second clock signal; and

said output port means conveying w words to said output data bus every n periods of said second clock signal.

2. The storage system according to claim 1 wherein the RAM and pipeline register in each of said storage sections are physically supported on a plurality of circuit board modules which are each supported in proximity to one another in a system chassis, each of said modules supporting a portion of the total RAM in each section, and wherein storage sections which have connected pipeline registers are positioned physically adjacent one another to minimize the distance between adjacent ones of said pipeline registers, and further wherein said means for connecting input registers and means for connecting output registers each include a plurality of conductors which are jumpered between adjacent pipeline registers.

3. The solid state storage system according to claim 1 wherein said RAM in each section is organized into a plurality of storage banks.

4. The storage system according to claim 3 wherein the banks of each section are paired and wherein each pair of banks share a single addressing network from said addressing means, and further wherein only one bank of each pair is referenced at a time.

5. The storage system according to claim 4 wherein said RAM comprises a plurality of memory chips having a matrix of individual one-bit storage locations which are addressable by row and column and wherein each word stored in said banks is stored in a plurality of chips, one bit per chip, with the same row and column storage location utilized in each chip.

6. The storage system according to claim 4 wherein said addressing means simultaneously sends the same address to the corresponding banks in each of said sections every s clock periods of said first and second clock signals in write and read operations respectively, so that words read or written on the same clock period are stored in corresponding memory locations.

7. The storage system according to claim 6 wherein said same addressing means sends the address to the corresponding banks in each section until each bank has stored one word in the location of said address, said address being sent to a different set of corresponding banks every s clock periods of said first and second clock signals during write and read operations, respectively.

8. The storage system according to claim 7 wherein said addressing means generates one new address every s clock periods of said first and second clock signals in write and read operations respectively, and wherein said addressing means includes means for delaying said address s clock periods of the respective clock signals and consequently conveying it to the next consecutive set of banks.

9. The storage system according to claim 5 wherein said RAM is dynamic and further including refresh means for periodically refreshing all said memory chips through said addressing means and addressing network, said refresh means causing said addressing means to reference one or more rows of internal chip addresses for refresh at a time, said refresh addresses delivered to the corresponding banks in each section with a different bank referenced every s clock periods of said first clock signal.

10. The storage system according to claim 9 further including a plurality of power supplies for supplying power to said RAM, the power requirement of said RAM distributed over said supplies to minimize worst case load on said supplies so that refresh noise spikes are minimized.