Lu, Jau-Hone; Lu, Shu-Ying; Lu, Chang-Ming; Hung, Ya-Ling;

Method of fabricating mixed-mode device

A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.

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What is claimed is:

1. A method of fabricating a mixed-mode device in a substrate having an isolation structure formed therein comprising the steps of:

forming a first gate oxide layer on the substrate;

forming a first conductive layer to cover a portion of the first gate oxide layer and a portion of the isolation structure;

patterning the first gate oxide layer with the first conductive layer serving as a mask until a portion of the substrate is exposed;

simultaneously forming a second gate oxide layer on an exposed portion of the substrate and forming an oxide layer abutting the first conductive layer without oxidizing the first gate oxide layer;

forming a second conductive layer to cover the second oxide layer and the oxide layer;

patterning the second conductive layer, wherein a remaining second conductive layer covers the second gate oxide layer and a part of the oxide layer;

patterning the oxide layer using the remaining second conductive layer as a mask; and

patterning the first conductive layer and the remaining second conductive layer covering the first gate oxide layer until the first gate oxide layer is exposed.

2. The method of claim 1, wherein a material of the first conductive layer comprises doped polysilicon.

3. The method of claim 1, wherein a material of the second conductive layer comprises doped polysilicon.

4. The method of claim 1, wherein the step of forming the first gate oxide layer comprises oxidation.

5. The method of claim 1, wherein the step of forming the second gate oxide layer and the oxide layer comprises oxidation.

6. A method of fabricating a mixed-mode device, which is suitable for a substrate having an isolation structure formed therein, comprising the steps of:

forming a first gate oxide layer on a substrate;

forming a first conductive layer to cover a portion of the first gate oxide layer and a portion of the isolation structure;

patterning the first gate oxide layer with the first conductive layer serving as a mask until a portion of the substrate is exposed;

simultaneously forming a second gate oxide layer on an exposed portion of the substrate and forming an oxide layer abutting the first conductive layer without oxidizing the first gate oxide layer;

forming a second conductive layer on the second gate oxide layer; and

patterning the first conductive layer and the second conductive layer to form a first gate and a second gate.

7. The method of claim 6, wherein a material of the second conductive layer comprises doped polysilicon.

8. The method of claim 6, wherein the step of forming the first gate oxide layer comprises oxidation.

9. The method of claim 6, wherein the step of forming the second gate oxide layer comprises oxidation.

10. A method of fabricating a mixed-mode device in a substrate having an isolation structure formed therein comprising the steps of:

forming a first gate oxide layer on the substrate;

forming a bottom electrode layer of a capacitor to cover a portion of the first gate oxide layer and a portion of the isolation structure;

patterning the first gate oxide layer with the bottom electrode layer serving as a mask until a portion of the substrate is exposed;

simultaneously forming a second gate oxide layer on an exposed portion of the substrate and an oxide layer abutting the bottom electrode layer without oxidizing the first gate oxide layer;

forming a conductive layer to cover the second gate oxide layer and the oxide layer;

patterning the conductive layer, wherein a remaining conductive layer covers the second gate oxide layer and a part of the oxide layer;

patterning the oxide layer using the remaining conductive layer as a mask, wherein the oxide layer serves as a dielectric layer of the capacitor; and

patterning the bottom electrode layer and the remaining conductive layer covering the first gate oxide layer until the first gate oxide layer is exposed, wherein the patterned conductive layer on the oxide layer serves as a top electrode layer of the capacitor and the patterned conductive layer on the first gate oxide layer serves as a gate electrode after the patterning step of the bottom electrode layer and the remaining conductive layer is performed.