Memory protection circuit

A memory protection circuit is provided which prevents data stored in a programmable memory from being destroyed due to uncontrolled operations or malfunction of a writing unit. The memory protection circuit comprises a first decoder for detecting first predetermined data from write data, a second decoder for detecting second predetermined data out of address data which is associated with the write data, and a latch for latching a detection output of the first decoder when both a detection output of the second decoder and a write command signal exist, and for selectively allowing and inhibiting the write data from being written in a memory based on the information being latched.

What is claimed is:

1. A protection circuit for a memory in which data from a processing device including a write control terminal may be written, comprising:

first decoder means for detecting a first pattern which is included in data to be written into said memory to produce a first detection output;

second decoder means for detecting a second pattern which is included in address data, to produce a second detection output; and

control means for enabling data to be written in said memory when both said first and second decoder means produce said first and second detection outputs, respectively, and for cancelling the enabled condition when said second decoder means produces said second detection output and said first decoder means does not produce said first detection output.

2. A protection circuit as claimed in claim 1, wherein said second decoder means comprises means for producing said second detection output when detecting said second pattern, and means for producing a third detection output when detecting an address of said memory out of said address data; and wherein said control means comprises NOR gate means receiving said second detection output and a write control signal applied from said write control terminal of said processing device to said memory, flip-flop means having a Q terminal output and also having a data terminal and a clock terminal to which said first detection output and the output of said NOR gate means are applied, respectively, and OR gate means receiving said write control signal and said Q terminal output of said flip-flop means for providing the output thereof to said write control terminal of said memory.

3. A protection circuit for a memory in which data from a processing device including a write control terminal may be written, comprising:

first decoder means for detecting a first pattern which is included in data to be written into said memory to produce a first detection output;

second decoder means for detecting a second pattern which is included in address data, to produce a second detection output; and

control means for enabling data to be written in said memory only for a predetermined period of time from an instant when both said first and second decoder means produce said first and second detection outputs, respectively.

4. A protection circuit as claimed in claim 3, wherein said second decoder means comprises means for producing said second detection output when detecting said second pattern, and means for producing a third detection output when detecting an address of said memory out of said address data; and wherein said control means comprises NOR gate means receiving said second detection output and a write control signal applied from said write control terminal of said processing device to said memory; timer means started in response to the output of said NOR gate means and having a timer time which is equal to said predetermined period of time; flip-flop means having a Q terminal output and also having a data terminal, a clock terminal and a set terminal to which the output of said first decoder means, the output of said NOR gate means and the output of said timer means are applied, respectively; and OR gate means receiving said write control signal and said Q terminal output of said flip-flop means for providing the output thereof to said write control terminal of said memory.

5. A protection circuit for a memory, comprising:

first decoder means for detecting first predetermined data out of data to be written into said memory to produce a first detection output;

second decoder means for detecting second predetermined data out of address data which is associated with the data to be written; and

latch means for latching said first detection output when both said second detection output and a write command signal are applied thereto and selectively allowing and for inhibiting data from being written in said memory based on the content being latched by said latch means.

6. A protection circuit as claimed in claim 5, further comprising timer means for restoring said latch means to a condition which has occurred before latching when a predetermined period of time elapses after said latch means has latched said first detection output.

7. A protection circuit for a memory, including a write control terminal and a chip select terminal, in which data from a processing device may be written, comprising:

first decoder means for detecting a first pattern which is included in data to be written into said memory;

second decoder means for detecting a second pattern which is included in address data; and

control means responsive to the outputs of said first and second decoder means for controlling the writing of data from said processing device into said memory.

8. A protection circuit as claimed in claim 7, wherein said control means controls, in response to the outputs of said first and second decoder means and to a write control signal fed from said processing device toward said memory, the writing of data into said memory on the basis of a condition representing the feed of said write control signal to said memory.

9. A protection circuit as claimed in claim 8, wherein said control means comprises NOR gate means receiving said write control signal and the output of said second decoder; flip-flop means having a Q terminal output and also having a data terminal and a clock terminal to which the output of said first decoder means and the output of said NOR gate means are applied, respectively; and OR gate means receiving said write control signal and said Q terminal output of said flip-flop means for providing the output thereof to said write control terminal of said memory.

10. A protection circuit as claimed in claim 9, wherein said second decoder means comprises means for detecting an address of said memory out of said address data to provide a detection output to said chip selector terminal of said memory.

11. A protection circuit as claimed in claim 7, wherein said control means comprises means responsive to the outputs of said first and second decoder means and to a write control signal fed from said processing circuit toward said memory, for controlling the writing of data into said memory on the basis of a condition representing the feed of a chip selector signal which is fed to said chip selector terminal of said memory.

12. A protection circuit as claimed in claim 11, wherein said second decoder means further comprises means for producing an address detection signal when detecting an address of said memory out of said address data, and wherein said control means comprises NOR gate means receiving said write control signal and the output of said second decoder; flip-flop means having a Q terminal output and also having a data terminal and a clock terminal to which the output of said first decoder means and the output of said NOR gate means are applied, respectively; AND gate means receiving said Q terminal output of said flip-flop means and a read control signal which is fed from said processing device toward said memory; and OR gate means receiving the output of said AND gate means and said address detection signal for providing the output thereof as said chip selector signal to said chip selector terminal.

13. A protection circuit as claimed in claim 7, wherein said processing device and said memory each comprises a terminal for inputting and outputting data serially, and wherein said control means comprises means responsive to the outputs of said first and second decoder means and to a write control signal from said processing device for controlling the writing of data into said memory on the basis of a condition representing the feed of a chip selector signal which is fed to said chip selector terminal of said memory.

14. A protection circuit as claimed in claim 13, wherein said control means comprises NOR gate means receiving said write control signal and the output of said second decoder means; and flip-flop means having a Q terminal output and also having a data terminal and a clock terminal to which the output of said first decoder means and the output of said NOR gate means are applied, respectively, for providing said Q terminal output thereof as said chip selector signal to said chip selector terminal.

15. A protection circuit as claimed in claim 7, wherein said processing device and said memory each comprise a terminal for inputting and outputting data serially and a serial clock terminal, and wherein said control means comprises means responsive to the outputs of said first and second decoder means and to a write control signal from said processing device for controlling the writing of data into said memory on the basis of a condition representing the feed of a serial clock which is fed from said processing device to said memory.

16. A protection circuit as claimed in claim 15, wherein said control means comprises NOR gate means receiving said write control signal and the output of said second decoder; flip-flop means having a data terminal and a clock terminal to which the output of said first decoder means and the output of said NOR gate means are applied, respectively; and AND gate means receiving said Q terminal output of said flip-flop means and said serial clock for providing the output thereof to said serial clock terminal of said memory.

17. A protection circuit for a memory including a write control terminal in which data from a processing device may be written, comprising:

first decoder means for detecting a first pattern which is included in data to be written in said memory;

second decoder means for detecting a second pattern which is included in address data; and

control means responsive to the detection outputs of said first and second decoder means for enabling data from said processing device to be written in said memory only for a predetermined period of time.

18. A protection circuit as claimed in claim 17, wherein said control means comprises means responsive to the outputs of said first and second decoder means and to a write control signal fed from said processing device to said memory for controlling the writing of data into said memory on the basis of a condition representing the feed of said write control signal to said memory.

19. A protection circuit as claimed in claim 18, wherein said control means comprises NOR gate means receiving said write control signal and the output of said second decoder means; timer means started in response to the output of said NOR gate means and having a timer time which is equal to said predetermined period of time; flip-flop means having a Q terminal output and also having a data terminal, a clock terminal and a set terminal to which the output of said first decoder means, the output of said NOR gate means and the output of said timer means are applied, respectively; and OR gate means receiving said write control signal and said Q terminal output of said flip-flop means for providing the output thereof to said write control terminal of said memory.

20. A method of protecting a memory in which data from a processing device may be written, comprising the steps of:

detecting a first pattern out of data to be written into said memory;

detecting a second pattern out of address data; and

controlling the writing of data from said processing device into said memory in response to detection of said first and second patterns.

21. A method as claimed in claim 20, wherein the step of controlling the writing comprises the steps of:

enabling said writing when both said first and second patterns are detected; and

cancelling the enabled condition when said second pattern is detected and said first pattern is not detected.

22. A method as claimed in claim 20, wherein the step of controlling the writing comprises the steps of:

enabling said writing when both said first and second patterns are detected; and

cancelling the enabled condition when a predetermined period time elapses after said writing has been enabled.