Ohashi, Masayuki;

Output buffer circuits

An output buffer circuit comprises a pair of first and second output MOS transistors coupled between a power supply line and a ground line; a booster circuit for boosting the power supply voltage up to a predetermined high voltage higher than a power supply voltage; a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors connected in series between an output side of the booster circuit and the ground line; and a level shifter circuit having a first terminal coupled to an output side of a first logic gate for receiving logic signals from the first logic gate, a second terminal coupled to the gates of the n-channel and p-channel MOS transistors of the complementary MOS circuit and a third terminal coupled to the output side of the booster circuit for receiving the predetermined high voltage from the booster circuit, the level shifter circuit performing to shift the logic signal of the logic gate up to at least almost the same level as the predetermined high voltage to supply a shifted up signal to the gates of the n-channel and p-channel MOS transistors of the complementary MOS circuit.

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What is claimed is:

1. A driver circuit coupled between an output side of a logic gate and a gate of a first output MOS transistor being paired with a second output MOS transistor for driving said gate of said first output MOS transistor according to logic signals from said logic gate, said first and second output MOS transistors forming an output buffer circuit, said first output MOS transistor being provided between a power supply line supplied with a power supply voltage and an output terminal of said output buffer circuit, said second output MOS transistor being provided between said output terminal and a ground line supplied with a ground potential, said second output MOS transistor being driven according to other logic signals from another logic gate, said driver circuit comprising:

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage independently from said logic signals from said logic gate;

a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and a ground line, said complementary MOS circuit having an output terminal coupled to said gate of said first output MOS transistor; and

a level shifter circuit having a first terminal coupled to said output side of said logic gate for receiving said logic signal from said logic gate, said level shifter circuit having a second terminal coupled to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit comprising:

a first p-channel MOS transistor having a gate coupled to said second terminal of said level shifter circuit, a drain and a source coupled to said third terminal of said level shifter circuit;

a second p-channel MOS transistor having a gate coupled to said drain of said first p-channel MOS transistor, a drain coupled to said second terminal of said level shifter circuit and a source coupled to said third terminal of said level shifter circuit;

a first n-channel MOS transistor having a gate coupled to said first terminal of said level shifter circuit, a drain coupled to said gate of said second p-channel MOS transistor and a source coupled to a ground line and a drain coupled to said drain of said first p-channel MOS transistor;

a second n-channel MOS transistor having a gate, a drain coupled to said second terminal of said level shifter circuit and a source coupled to a ground line; and

an inverter logic circuit having an input terminal coupled to said third terminal of said level shifter circuit and an output terminal coupled to said gate of said second n-channel MOS transistor.

2. The driver circuit as claimed in claim 1, wherein said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor and said n-channel MOS transistor has a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor.

3. A driver circuit coupled between an output side of a logic gate and a gate of a first output MOS transistor being paired with a second output MOS transistor for driving said gate of said first output MOS transistor according to logic signals from said logic gate, said first and second output MOS transistors forming an output buffer circuit, said first output MOS transistor being provided between a power supply line supplied with a power supply voltage and an output terminal of said output buffer circuit, said second output MOS transistor being provided between said output terminal and a ground line supplied with a ground potential, said second output MOS transistor being driven according to other logic signals from another logic gate, said driver circuit comprising:

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage independently from said logic signals from said logic gate;

a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and a ground line, said complementary MOS circuit having an output terminal coupled to said gate of said first output MOS transistor; and

a level shifter circuit having a first terminal coupled to said output side of said logic gate for receiving said logic signal from said logic gate, said level shifter circuit having a second terminal coupled to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit comprising:

a first p-channel MOS transistor having a gate coupled to said second terminal of said level shifter circuit, a drain and a source coupled to said third terminal of said level shifter circuit;

a second p-channel MOS transistor having a gate coupled to said drain of said first p-channel MOS transistor, a drain coupled to said second terminal of said level shifter circuit and a source coupled to said third terminal of said level shifter circuit;

a first n-channel MOS transistor having a gate coupled to said first terminal of said level shifter circuit, a drain coupled to said gate of said second p-channel MOS transistor and a source coupled to a ground line and a drain coupled to said drain of said first p-channel MOS transistor;

a second n-channel MOS transistor having a gate coupled to said power supply line, a drain coupled to said first terminal of said level shifter circuit and a source coupled to said second terminal of said level shifter circuit.

4. The driver circuit as claimed in claim 3, wherein said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor and n-channel MOS transistor has a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor.

5. A driver circuit coupled between an output side of a logic gate and a gate of a first output MOS transistor being paired with a second output MOS transistor for driving said gate of said first output MOS transistor according to logic signals from said logic gate, said first and second output MOS transistors forming an output buffer circuit, said first output MOS transistor being provided between a power supply line supplied with a power supply voltage and an output terminal of said output buffer circuit, said second output MOS transistor being provided between said output terminal and a ground line supplied with a ground potential, said second output MOS transistor being driven according to other logic signals from another logic gate, said driver circuit comprising:

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage independently from said logic signals from said logic gate;

a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and a ground line, said complementary MOS circuit having an output terminal coupled to said gate of said first output MOS transistor; and

a level shifter circuit having a first terminal coupled to said output side of said logic gate for receiving said logic signal from said logic gate, said level shifter circuit having a second terminal coupled to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit,

said first output MOS transistor being an n-channel MOS transistor having a source coupled to said power supply line, a drain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit, and said second output MOS transistor being an n-channel MOS transistor having a source coupled to said ground line, a drain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit.

6. The driver circuit as claimed in claim 5, wherein said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor and n-channel MOS transistor has a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor.

7. An output buffer circuit comprising:

a pair of first and second output MOS transistors, said first output MOS transistor having a source coupled to a power supply line supplied with a power supply voltage, a drain coupled to an output terminal and a gate and said second output MOS transistor having a source coupled to a ground line supplied with a ground voltage, a drain coupled to said output terminal and a gate;

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage;

a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and said ground line, said complementary MOS circuit having an output terminal coupled to said gate of said first output MOS transistor;

a level shifter circuit having a first terminal coupled to an output side of a first logic gate for receiving logic signals from said first logic gate, said level shifter circuit having a second terminal coupled to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit comprising:

a first p-channel MOS transistor having a gate coupled to said second terminal of said level shifter circuit, a drain and a source coupled to said third terminal of said level shifter circuit;

a second p-channel MOS transistor having a gate coupled to said drain of said first p-channel MOS transistor, a drain coupled to said second terminal of said level shifter circuit and a source coupled to said third terminal of said level shifter circuit;

a first n-channel MOS transistor having a gate coupled to said first terminal of said level shifter circuit, a drain coupled to said gate of said second p-channel MOS transistor and a source coupled to a ground line and a drain coupled to said drain of said first p-channel MOS transistor;

a second n-channel MOS transistor having a gate, a drain coupled to said second terminal of said level shifter circuit and a source coupled to a ground line;

an inverter logic circuit having an input terminal coupled to said third terminal of said level shifter circuit and an output terminal coupled to said gate of said second n-channel MOS transistor; and

an inverter logic circuit having an output terminal coupled to said gate of said second output MOS transistor and an input terminal coupled to a second logic gate.

8. The output buffer circuit as claimed in claim 7, wherein said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor and said n-channel MOS transistor has a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor.

9. The output buffer circuit as claimed in claim 7, wherein said first and second output MOS transistors are an n-channel type.

10. An output buffer circuit comprising:

a pair of first and second output MOS transistors, said first output MOS transistor having a source coupled to a power supply line supplied with a power supply voltage, a drain coupled to an output terminal and a gate and said second output MOS transistor having a source coupled to a ground line supplied with a ground voltage, a drain coupled to said output terminal and a gate;

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage;

a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and said ground line, said complementary MOS circuit having an output terminal coupled to said gate of said first output MOS transistor;

a level shifter circuit having a first terminal coupled to an output side of a first logic gate for receiving logic signals from said first logic gate, said level shifter circuit having a second terminal coupled to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said gates of said n-channel and p-channel MOS transistors of said complementary MOS circuit, said level shifter circuit comprising:

a first p-channel MOS transistor having a gate coupled to said second terminal of said level shifter circuit, a drain and a source coupled to said third terminal of said level shifter circuit;

a second p-channel MOS transistor having a gate coupled to said drain of said first p-channel MOS transistor, a drain coupled to said second terminal of said level shifter circuit and a source coupled to said third terminal of said level shifter circuit;

a first n-channel MOS transistor having a gate coupled to said first terminal of said level shifter circuit, a drain coupled to said gate of said second p-channel MOS transistor and a source coupled to a ground line and a drain coupled to said drain of said first p-channel MOS transistor;

a second n-channel MOS transistor having a gate coupled to said power supply line, a drain coupled to said first terminal of said level shifter circuit and a source coupled to said second terminal of said level shifter circuit; and

an inverter logic circuit having an output terminal coupled to said gate of said second output MOS transistor and an input terminal coupled to a second logic gate.

11. The output buffer circuit as claimed in claim 10, wherein said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor and said n-channel MOS transistor has a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor.

12. The output buffer circuit as claimed in claim 10, wherein said first and second output MOS transistors are an n-channel type.

13. A driver circuit coupled between an output side of a logic gate and a gate of a first output MOS transistor being paired with a second output MOS transistor for driving said gate of said first output MOS transistor according to logic signals from said logic gate, said first and second output MOS transistors forming an output buffer circuit, said first output MOS transistor being provided between a power supply line supplied with a power supply voltage and an output terminal of said output buffer circuit, said second output MOS transistor being provided between said output terminal a ground line supplied with a ground potential, said second output MOS transistor being driven according to another logic signals from another logic gate, said driver circuit comprising:

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage independently from said logic signals from said logic gate;

a switching circuit coupled between said output side of said booster circuit and a ground line supplied with a ground potential, said switching circuit having an input terminal for receiving a switch control signal, according to which said switching circuit performs a switching operation to supply either said predetermined high voltage or said ground voltage to said gate of said first output MOS transistor, said switching circuit comprising a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and said ground line, said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain connected to said output terminal coupled to said gate of said first MOS transistor, said n-channel MOS transistor having a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor; and

a level shifter circuit having a first terminal coupled to said output side of said logic gate for receiving said logic signal from said logic gate, said level shifter circuit having a second terminal coupled to said input terminal of said switching circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said input terminal of said switching circuit, said level shifter circuit comprising:

a first p-channel MOS transistor having a gate coupled to said second terminal of said level shifter circuit, a drain and a source coupled to said third terminal of said level shifter circuit;

a second p-channel MOS transistor having a gate coupled to said drain of said first p-channel MOS transistor, a drain coupled to said second terminal of said level shifter circuit and a source coupled to said third terminal of said level shifter circuit;

a first n-channel MOS transistor having a gate coupled to said first terminal of said level shifter circuit, a drain coupled to said gate of said second p-channel MOS transistor and a source coupled to a ground line and a drain coupled to said drain of said first p-channel MOS transistor;

a second n-channel MOS transistor having a gate, a drain coupled to said second terminal of said level shifter circuit and a source coupled to a ground line; and

an inverter logic circuit having an input terminal coupled to said third terminal of said level shifter circuit and an output terminal coupled to said gate of said second n-channel MOS transistor.

14. The drive circuit as claimed in claim 13, wherein said first output MOS transistor is an n-channel MOS transistor having a source coupled to said power supply line, a drain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit and said second output MOS transistor is an n-channel MOS transistor having a source coupled to said ground line, a drain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit.

15. A driver circuit coupled between an output side of a logic gate and a gate of a first output MOS transistor being paired with a second output MOS transistor for driving said gate of said first output MOS transistor according to logic signals from said logic gate, said first and second output MOS transistors forming an output buffer circuit, said first output MOS transistor being provided between a power supply line supplied with a power supply voltage and an output terminal of said output buffer circuit, said second output MOS transistor being provided between said output terminal a ground line supplied with a ground potential, said second output MOS transistor being driven according to another logic signals from another logic gate, said driver circuit comprising:

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage independently from said logic signals from said logic gate;

a switching circuit coupled between said output side of said booster circuit and a ground line supplied with a ground potential, said switching circuit having an input terminal for receiving a switch control signal, according to which said switching circuit performs a switching operation to supply either said predetermined high voltage or said ground voltage to said gate of said first output MOS transistor, said switching circuit comprising a complementary MOS circuit comprising a pair of n-channel and p-channel MOS transistors, both of which are connected in series between an output side of said booster circuit and said ground line, said p-channel MOS transistor has a source coupled to said output side of said booster circuit and a drain connected to said output terminal coupled to said gate of said first MOS transistor, said n-channel MOS transistor having a source coupled to said ground line and a drain coupled to said output terminal coupled to said gate of said first output MOS transistor; and

a level shifter circuit having a first terminal coupled to said output side of said logic gate for receiving said logic signal from said logic gate, said level shifter circuit having a second terminal coupled to said input terminal of said switching circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said input terminal of said switching circuit, said level shifter circuit comprises:

a first p-channel MOS transistor having a gate coupled to said second terminal of said level shifter circuit, a drain and a source coupled to said third terminal of said level shifter circuit;

a second p-channel MOS transistor having a gate coupled to said drain of said first p-channel MOS transistor, a drain coupled to said second terminal of said level shifter circuit and a source coupled to said third terminal of said level shifter circuit;

a first n-channel MOS transistor having a gate coupled to said first terminal of said level shifter circuit, a drain coupled to said gate of said second p-channel MOS transistor and a source coupled to a ground line and a drain coupled to said drain of said first p-channel MOS transistor;

a second n-channel MOS transistor having a gate coupled to said power supply line, a drain coupled to said first terminal of said level shifter circuit and a source coupled to said second terminal of said level shifter circuit.

16. The drive circuit as claimed in claim 15, wherein said first output MOS transistor is an n-channel MOS transistor having a source coupled to said power supply line, a chain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit and said second output MOS transistor is an n-channel MOS transistor having a source coupled to said ground line, a drain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit.

17. A driver circuit coupled between an output side of a logic gate and a gate of a first output MOS transistor being paired with a second output MOS transistor for driving said gate of said first output MOS transistor according to logic signals from said logic gate, said first and second output MOS transistors forming an output buffer circuit, said first output MOS transistor being provided between a power supply line supplied with a power supply voltage and an output terminal of said output buffer circuit, said second output MOS transistor being provided between said output terminal a ground line supplied with a ground potential, said second output MOS transistor being driven according to another logic signals from another logic gate, said driver circuit comprising:

a booster circuit for boosting said power supply voltage up to a predetermined high voltage higher than said power supply voltage, said booster circuit keeping an output at said predetermined high voltage independently from said logic signals from said logic gate;

a switching circuit coupled between said output side of said booster circuit and a ground line supplied with a ground potential, said switching circuit having an input terminal for receiving a switch control signal, according to which said switching circuit performs a switching operation to supply either said predetermined high voltage or said ground voltage to said gate of said first output MOS transistor; and

a level shifter circuit having a first terminal coupled to said output side of said logic gate for receiving said logic signal from said logic gate, said level shifter circuit having a second terminal coupled to said input terminal of said switching circuit, said level shifter circuit also having a third terminal coupled to said output side of said booster circuit for receiving said predetermined high voltage from said booster circuit, said level shifter circuit shifting said logic signal of said logic gate up to at least almost the same level as said predetermined high voltage to supply a shifted up signal to said input terminal of said switching circuit, said first output MOS transistor is an n-channel MOS transistor having a source coupled to said power supply line, a chain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit and said second output MOS transistor is an n-channel MOS transistor having a source coupled to said ground line, a drain coupled to said output terminal and a gate coupled to said second terminal of said level shifter circuit.