On chip decoupling capacitor

The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second electrode is a common electrode to a second decoupling capacitor overlying and thereby coupled in parallel to said first decoupling capacitor. The second capacitor's first electrode is the common electrode and its second electrode is made of conductively doped polysilicon. The electrodes made of the conductively doped polysilicon may be further enhanced by forming a silicided material, such as tungsten silicide, thereon. The decoupling capacitors' dielectric can be formed from high dielectric constant materials, such as TEOS, oxide, nitride or any combination thereof. The second decoupling capacitor could be fabricated over field oxide and used as a single capacitor having a first and second conductively doped polysilicon electrodes (either silicided or non-silicided) with a capacitor dielectric sandwiched in between.

We claim:

1. A method for forming a decoupling capacitor structure comprising a first decoupling capacitor and a second decoupling capacitor fabricated on a conductive substrate surface comprising the steps of:

a) forming a first insulating layer over said conductive substrate surface;

b) forming a first conductive layer over said first insulating layer;

c) patterning said first conductive layer and said first insulating layer thereby resulting in patterned edges on said first conductive layer and said first insulating layer, said patterning further forms said first decoupling capacitor, wherein said conductive substrate serves as a first capacitor plate, said first conductive layer serves as a second capacitor plate and said first insulating layer serves as an insulator therebetween;

d) forming diffusion areas aligned to the patterned edges of said first conductive layer and said insulating layer;

e) forming insulating spacers adjacent said patterned edges;

f) forming a second insulating layer over the patterned first conductive layer;

g) forming a second conductive layer over said second insulating layer; and

h) patterning said second conductive layer and said second insulating layer to form a second decoupling capacitor, wherein said first capacitor's second plate serves as a first capacitor plate to said second decoupling capacitor, said second conductive layer serves as said second decoupling capacitor's second capacitor plate and said second insulating layer serves as an insulator therebetween.

2. The method of claim 1, wherein a layer of silicided material is formed on at least one of said first and second conductive layers.

3. The method of claim 2, wherein a layer of silicided material is formed on both said first and second conductive layers.

4. The method of claim 2, wherein silicided material is tungsten silicide.

5. The method of claim 3, wherein silicided material is tungsten silicide.

6. The method of claim 1, wherein said first insulating layer is silicon oxide.

7. The method of claim 1, wherein said second insulating layer comprises a dielectric material selected from the group consisting of TEOS, silicon oxide, silicon oxide and any combination thereof.

8. A method for forming a decoupling capacitor structure comprising a first decoupling capacitor and second decoupling capacitor fabricated on a conductive silicon substrate of an integrated circuit comprising the steps of:

a) forming a first insulating layer over said conductive substrate surface;

b) forming a first conductive polysilicon layer over said first insulating layer;

c) patterning said first conductive polysilicon layer and said first insulating layer thereby resulting in patterned edges on said first conductive layer and said first insulating layer, said patterning further forms said first decoupling capacitor, wherein said conductive substrate serves as a first capacitor plate, said first conductive serves as a second capacitor plate and said first insulating layer serves as a first capacitor dielectric therebetween;

d) implanting conductive impurities into said conductive silicon substrate thereby forming diffusion areas aligned to the patterned edges of said first conductive polysilicon layer and said insulating layer;

e) forming insulating spacers adjacent said patterned edges;

f) depositing a second insulating layer over the patterned first conductive polysilicon layer;

g) depositing a second conductive polysilicon layer over said second insulating layer; and

h) patterning said second conductive polysilicon layer and said second insulating layer for form a second decoupling capacitor, said second decoupling capacitor, wherein said first capacitor's second plate serves as a first capacitor plate to said second decoupling capacitor, said second conductive layer serves as said second decoupling capacitor's second capacitor plate and said second insulating layer serves as a second capacitor dielectric therebetween.

9. The method of claim 8, wherein a layer of silicided material is formed on at least one of said first and second conductively doped polysilicon layers.

10. The method of claim 8, wherein a layer of silicided material is formed on both said first and second conductively doped polysilicon layers.

11. The method of claim 9, wherein silicided material comprises tungsten silicide.

12. The method of claim 10, wherein silicided material comprises tungsten silicide.

13. The method of claim 8, wherein said first capacitor dielectric is silicon oxide.

14. The method of claim 8, wherein said second capacitor dielectric comprises a dielectric material selected from the group consisting of TEOS, silicon oxide, silicon nitride and any combination thereof.