Distributed crossbar switch architecture

A switching array as described for connecting ones of a plurality of data sources to ones of a plurality of data sinks. The array includes source data busses which transmit from a connected source, data words, a connection mask and a connection designator. The connection mask has bit positions that map to individual data sinks. A multiplexer/control circuit module is associated with each individual data sink for controlling the interconnection of the data sink to a source data bus. Each multiplexer/control circuit module is connected to each source data bus and is responsive to an active state connection mask bit and a connection designator on a first source data bus, to establish a connection between an associated sink and the first source data bus. This configuration enables the multiplexer/control circuit module to establish a connection without reference to any other multiplexer/control circuit.

We claim:

1. A distributed crossbar switching array for substantially simultaneously connecting data sources to one or more of a plurality of data sinks available for connection, said distributed crossbar switching array comprising:

a source data bus connected to each said data source, for transmitting from a connected data source, data words, a connection mask and a connection signal, said connection mask having plural bit positions that map to plural data sinks, a said connection mask and connection signal transmitted in parallel and concurrently; and

a multiplexer/control means associated with and connected to each data sink and to each source data bus, for providing connection of an associated data sink to a connected source data bus, each said multiplexer/control means simultaneously monitoring each said connected source data bus and responsive to manifestations on a connected source data bus of a connection signal and a connection mask bit position that is in an active state and maps to the data sink associated with said multiplexer/control means, to create a circuit connection between said associated data sink and said connected source data bus.

2. The switching array of claim 1, wherein each said multiplexer/control means comprises;

multiplexer means for providing connection between each said source data bus and a data sink connected to said multiplexer/control means; and

logic means connected to each said source data bus, for issuing an interconnect signal to said multiplexer means to make connection between a said associated data sink and a data source via a source data bus, said interconnect signal issued in response to a manifestation on a said source data bus of a connection signal and a connection mask having an active state bit position that maps to said associated data sink, said interconnect signal issued when said logic means receives an available signal from said associated data sink.

3. The switching array of claim 2, wherein each said source data bus has an assigned priority value, and a said logic means issues said interconnect signal to a said multiplexer means only when no higher priority source data bus manifests a connection signal.

4. The switching array of claim 3, wherein said data sources impress data words on connected source data busses once per clock cycle, a data source also impressing on a connected source data bus, a connection mask and a connection signal simultaneously during a clock cycle whereby a said logic means in response thereto, is enabled to issue said interconnect signal during said clock cycle.

5. The switching array of claim 4, wherein said connection mask is an N-bit data word, where N equals the number of data sinks, and said connection signal is manifested by a bit state appended to said N-bit data word.

6. The switching array of claim 5, wherein each said logic means includes ARB bit logic, said ARB bit logic enabling a determination to be made of the highest priority data source which, in any clock cycle, manifests a connection signal on a source data bus connected thereto, each said source data bus exhibiting the priority of its connected data source, said ARB bit logic comprising:

AND means coupled to a line in each source data bus that manifests said connection signal, for generating an ARB signal for one said source data bus; and

inhibitory logic means coupled to lines in all higher priority source data busses that manifest connection signals, for inhibiting said AND means from generating an ARB signal for a connected source data bus if any higher priority source data bus manifests a connection signal.

7. The switching array of claim 6 wherein said multiplexer means is a multiplexer having M sets of inputs, where M equals the number of source data busses, one set of inputs from each said source data bus comprising at least N+1 lines, each said logic means comprising:

N latches, one each for generating an interconnection signal corresponding to a different source data bus; and

N AND gates, one each feeding a Set input to an associated one of said latches, each AND gate having at least three inputs, one for receiving an Available state signal from the logic means associated with said data sink, a second for receiving the signal state of a Connection mask bit on a source data bus and a third for receiving an ARB signal from said AND means.

8. The switching array of claim 1 wherein each said source data bus includes at least N+1 conductors, wherein N is the number of data sinks.

9. The switching array of claim 1, wherein each said source data bus includes a subset of N+1 conductors, where N is the number of data sinks, each said data source including time division multiplex means for impressing on said subset of conductors, data words and a connection mask, said multiplex means multiplexing subsets of N+1 bits of a said word or mask a number of times until all N+1 bits have been placed on a source data bus.

10. The switching array of claim 1, wherein each said data source transmits on a connected source data bus a connection clear signal, said connection clear signal transmitted in parallel and concurrently with a said connection mask, each said multiplexer/control means responsive to manifestations on a coupled source data bus of a connection clear signal and a said connection mask bit position that is in an active state and maps to the data sink associated with said multiplexer/control means, to disconnect said associated data sink from said connected source data bus.

11. The switching array of claim 3, wherein each said logic means includes ARB bit logic, each said ARB bit logic enabling a determination to be made of the highest priority source which, in any clock cycle, causes a said connection signal to be manifest in combination with an asserted connection mask bit that maps to a sink associated with said ARB bit logic, said ARB bit logic comprising:

AND means coupled to lines in each source data bus that manifest said connection signal and said asserted mask bit that maps to the associated sink, for generating an ALLOC signal indicating an attempted allocation of said associated sink; and

inhibitory logic means coupled to lines in all higher priority source data busses that manifest said connection signals and a mask bit that maps to said associated sink, for inhibiting said ALLOC signal if any higher priority data bus manifests an attempt to allocate said associated sink.

12. The switching array of claim 11, wherein said data sources are adapted impress data words on connected source data busses once per clock cycle, a data source impressing a said connection mask and a connection signal simultaneously during a clock cycle on a connected source data bus, whereby a said logic means in response thereto, is enabled to issue said interconnect signal during said clock cycle.

13. The switching array of claim 12, wherein said multiplex means is pipelined and comprises:

an input register connected to each source data bus, there being N such input registers, where N equals the number of source data busses;

gating means for gating an input register in response to an interconnect signal from said logic means, said interconnect signal corresponding to the source data bus connected to said gated input register;

OR register means for combining outputs from said gating means into an output register, said output register receiving only data gated through said gating means by said interconnect signal; and

means for sequentially operating said input register gating means and OR register means to create a pipeline data flow.