Trigger pulse generator circuit
A trigger pulse generator circuit for converting an input pulse into a sharp pulse to be used as a trigger pulse is disclosed. The input pulse is applied to a first and a second switching means which are connected in cascade, the second switching means having a larger delay time than that of the first switching means. An output trigger pulse is derived from a connecting point of the first and second switching means. The first switching means becomes cut-off in response to the removal of the input pulse, while the second switching means becomes cut-off a predetermined time after the removal of the input pulse due to a time delay caused by the storage time of a transistor of the second switching means. In consequence, a sharp trigger pulse is derived from the output terminal. Preferably, a discharging means for the charge stored in the second switching means is further provided between the ground and the second switching means. This trigger pulse generator circuit is advantageous in that no capacitive element is necessitated, and so it is quite suitable for application to an integrated circuit.
FIELD OF THE INVENTION
The present invention relates to a circuit for generating driving pulses for a pulse circuit, and more particularly to a trigger pulse generator circuit for generating trigger pulses.
BACKGROUND OF THE INVENTION
Trigger pulses are generally used for synchronizing a multi-vibrator and also for driving other pulses circuits.
Heretofore, the most conventional circuit for obtaining a pulse having a pulse width suitable for synchronization and/or driving has been a differentiating circuit composed of a capacitor and a resistor. In order to integrate circuits including such a differentiating circuit, it is necessary to provide terminals for externally mounting a capacitor. The alternative circuit suitable for a digital IC has been proposed for such purposes. In such a trigger pulse generator circuit, an output pulse obtained as a result of delaying an input pulse through an integrated circuit and the original input pulse are applied respectively to two inputs of an AND-circuit to derive at its output a trigger pulse having a pulse width corresponding to the overlapping time intervals of the two input signals. However, even in this case, a capacitor and its external mounting terminals are necessitated.
As described above, the trigger pulse generator circuits in the prior art were associated with various disadvantages due to the use of a capacitor, and so they were not suitable for circuit integration, in particular for semiconductor IC, and also were not simple in handling.
SUMMARY OF THE INVENTION
Therefore, it is a principal object of the present invention to provide a trigger pulse generator circuit without making use of a capacitor, and thereby to resolve the aforementioned various problems.
In order to achieve the above object, the inventor has constructed a trigger pulse generator circuit by making use of the charge storage effect of a transistor.
In the trigger pulse generator circuit according to the present invention, an input pulse is applied to a first and a second switching means which are connected to cascade, the second switching means having a larger delay time than that of the first switching means. As a result, an output trigger pulse is derived from a connecting point of the first and second switching means owing to the difference between the delay times of the first and second switching means. The second switching means in preferred and practicable embodiments, includes a switching element connected to the first switching means in cascade and a control element for controlling the operation of the switching element. During the rise time of the input pulse and also during the periods of time when the input pulse is present or absent, the output terminal is held at a low potential. During the fall time of the input pulse, the second switching means changes into the cut-off state a predetermined time after the change of the first switching means into the cut-off state, the predetermined time being equal to the storage time of a transistor of the second switching means. In consequence, a sharp trigger pulse is derived from the output terminal.
A discharging means for the charge stored in the second switching means is preferably added between the ground and the second switching means in order to warrant a reliable operation regardless of the value of a load impedance.
The above-featured trigger pulse generator circuit requires neither a differentiating circuit nor an integrating circuit nor a capacitor. Therefore, the trigger pulse generator circuit according to the present invention is suitable for circuit integration, and easy in handling, and in addition it can provide various other inherent advantages.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 is a schematic circuit diagram showing a first embodiment of the trigger pulse generator circuit according to the present invention;
FIG. 2 is a waveform diagram showing voltage and current waveforms at various points in the trigger pulse generator circuit of FIG. 1 for explaining the operation of the circuit; and
FIG. 3 is a schematic circuit diagram showing a second embodiment of the trigger pulse generator circuit according to the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Now the present invention will be described in more detail in connection with its preferred embodiments illustrated in the accompanying drawings. Referring first to FIG. 1, a first embodiment of the trigger pulse generator circuit according to the present invention is schematically shown. In this figure, the emitter electrodes of NPN transistors 1 and 3 are connected in common to the ground, and their respective base electrodes are connected to a common signal input terminal through a resistor 4 and a resistor 5, respectively. The collector electrode of the transistor 3 is connected through a series connection of resistors 6 and 7 to an ungrounded terminal of a power supply (not shown). The junction point between the resistors 6 and 7 is connected to the base electrode of a PNP transistor 2 whose emitter electrode is connected to the ungrounded terminal of the power supply. The collector electrode of the transistor 1 is connected through a resistor 8 to the collector electrode of the transistor 2. The collector electrode of the transistor 1 is also grounded through a resistor 9 sufficiently larger than the resistor 8 but low enough to discharge the charge stored in the transistor 2 quickly thus resulting in a pulse of smaller width than the input pulse. The respective resistance values are selected in such a manner that when the aforementioned circuit has been actuated in response to a predetermined input signal, the respective transistors may operate in their saturated ranges upon conducting.
It is to be noted that, when a load element (not shown) connected to the output terminal has an impedance equal to the above-mentioned value required for in the resistor 9, the resistor 9 may be eliminated. In other words, due to the resistor 9, the sharp trigger pulse can be derived from the circuit regardless of the load impedance. FIG. 2 is a waveform diagram for assisting the explanation of the operation of the circuit having the above-described construction, in which a voltage waveform of an input signal applied to the input terminal is represented at e.sub.i, current waveforms of the currents flowing through the transistors 1 and 2 are represented at i.sub.1 and i.sub.2, respectively, and an output voltage waveform is represented at e.sub.o. If the input signal e.sub.i is applied to the input terminal, the collector current of the transistor 3 increases to its saturations level after a predetermined period of time, that is, after a period equal to the sum of a delay time t.sub.d and a rise time t.sub.r of the input pulse. Since the base potential of the transistor 2 is determined by the collector current of the transistor 3, the collector current i.sub.2 of the transistor 2 increases to its saturation level after a further delay of a predetermined time. Though the base potential of the transistor 1 is placed under the same condition as the base potential of the transistor 3, the collector current of the transistor 1 cannot flow unless and until the transistor 2 becomes conducting. When the collector current of the transistor 1 reaches its saturation level, it short-circuits across the resistor 9, although a small voltage would appear across the resistor 9 due to a voltage drop across the collector-emitter path of the transistor 1 upon saturation.
When the input signal voltage e.sub.i becomes zero, that is, at the trailing edge of the input signal waveform, the base potentials of the transistors 1 and 3, respectively, become zero, while the collector currents i.sub.1 and i.sub.3 of the transistors 1 and 3, respectively, would become zero after a delay of a predetermined time, equal to the sum of a storage time t.sub.s and a falling time t.sub.f of the input pulse. Since the base potential of the transistor 2 is determined by the collector current i.sub.3 of the transistor 3, the collector current i.sub.2 of the transistor 2 tends to become zero after a further delay of a predetermined time. However, since the transistor 1 has been already switched to its cut-off state at that time, the collector current, that is, the current caused by the charge storage effect of the transistor 2 flows through the resistor 9. Accordingly, a sharp pulse voltage having a peak value substantially equal to the power supply voltage would appear across the resistor 9, because the resistance value of the resistor 9 is selected sufficiently larger than that of the resistor 8 as described previously. Since the storage time of the transistor 2 is determined by the resistor 9, the pulse width of the trigger pulse is varied in accordance with the resistance value of the resistor 9, with the width increasing the resistance value in increased and vice versa.
A second embodiment of the pulse generator circuit according to the present invention, which has been constructed by partly modifying the pulse generator circuit of FIG. 1, is illustrated in FIG. 3. In more particular, the part corresponding to the transistor 2 in FIG. 1 is replaced by a Darlington connection of transistors 22 and 23, which is deemed to be equivalent to one transistor having a large current amplification factor. If the circuit is constructed in the above-described modified form, then the storage time t.sub.s can be further prolonged, and it becomes possible to obtain a trigger pulse having a pulse width larger than that in the case of the first embodiment. A transistor 11 achieves the same function as the above-described transistor 1, and a transistor 13 achieves the same function as the above-described transistor 3. In addition, a circuit element equivalent to that shown in FIG. 1 is designated by a reference numeral formed by adding 10 to the corresponding reference numeral in FIG. 1. A transistor 25 is a transistor used for impedance matching, and the output pulse is derived from an emitter load 26 for the transistor 25. In this modified circuit also, the pulse width of the output pulse can be varied by changing the resistance value of a resistor 24 connected between the emitter of the transistor 23 and the ground.
As will be appreciated from the above-described embodiments, the circuit according to the present invention requires no capacitor, and also has various advantages such that adjustment and/or presetting of the pulse width of an output sharp trigger pulse are possible.
While transistors of specific conduction types have been used in the illustrated embodiments, it is possible to replace these transistors by transistors of opposite conduction types, and also it is possible to replace the transistors by other switching elements. Therefore, the scope of the invention should not be limited to the embodiments as described above and illustrated in the accompanying drawings, but it should be defined only by the appended claims.