# Fractional binary to decimal converter

 Fowler, Robert W.;

The present invention relates to a simplified apparatus for converting a ary fraction input into a Natural Binary Coded Decimal (8421 code) and subsequently into a decimal output with the proper sign. The invention provides means for selectively shifting and summing the binary fraction to effect a multiplication by ten. An integer portion to the left of a fixed binal point and a remaining fraction portion to the right are produced. The integer portion is extracted as a BCD character which is converted via a nixie display into decimal form. Shifting and summing successive remaining fractions and displaying successive integer portions produces a final decimal number which corresponds to the binary fraction input.

BACKGROUND OF THE INVENTION

Because the scientific and business worlds operate in a decimal system while the overwhelming majority of digital computers operate in a binary system (binary logic being cheaper, more reliable, and simpler), many apparatuses and methods have been devised for converting binary fractions to Binary Coded Decimal (BCD) or decimal form. However, these prior art approaches have been complex and have required intricate circuitry in performing the conversion. One such apparatus is outlined in U.S. Pat. No. 3,257,547. The converter therein described includes elegant logic units which successively multiply a fractional binary input by the decimal number ten (1010 in binary form) and then take the four most significant bits resulting from each multiplication process as the next most significant BCD digit of the output. In accomplishing this conversion, the described prior art apparatus executes two cycles, i.e., a shift cycle and a fix-up cycle. In operation, a fractional binary number to be converted is shifted out, one bit each cycle, least significant bit first, into a series of BCD units each having four flip-flops arranged to represent the binary coded decimal digit. During the fix-up cycle, the most significant bit of the four bits which enter each BCD unit is examined and, if it is a binary 1, an appropriate logically-determined number is subtracted from the shifted out number with the result being placed in the four flip-flops in BCD form. By employing these two cycles alternately, a complete binary to BCD conversion is effected in a number of cycles equal to the number of initial binary bits in the binary number.

The described prior art converter requires logic units which operate on the binary fraction in accordance with a series of Boolean equations. For example, according to the Boolean equations, the conversion of 1/16 (.0001 in binary) would include a first step shifting the least significant bit, 1, into the most significant digit flip-flop of a first four-digit BCD unit which reads the resulting BCD number as 8 (1000 in binary). By Boolean methods, the converter "fixes up" the resulting BCD number by subtracting 3 (0011 in binary) from 8 (1000 in binary) to give 5 (0101 in binary) in the most significant BCD unit. At this point in the conversion the BCD units together hold a value .5000 . . . . The 5 is then shifted to the most significant digit flip-flop of a second, third, and successive units (as more significant bits of the binary fraction word are shifted in) until it ends up in the --5-- position. After a number of other logical operations, a final decimal equivalent value of .0625 . . . is extracted corresponding to the initial binary .0001 (1/16). The logic units to "fix-up the BCD number and the gating networks, which implement the Boolean equations, greatly complicate the operation of this prior art converter.

SUMMARY OF THE INVENTION

The present invention converts binary number input into decimal outputs in a manner which is simpler and more versatile than that of the prior art, no implemented Boolean logic circuitry being required by the present invention.

In addition, the present invention provides means for determining decimal outputs, with appropriate sign designations, for positive and negative binary inputs.

The present invention also provides "manual" and "automatic" modes for setting the period between decimal readouts for a series of binary inputs.

In its preferred embodiment, the present invention contemplates the conversion of a 24-bit binary fraction into a ten-place decimal which results in a ten-fold increase in accuracy over prior conventional eight-place decimal outputs.

Lastly, the present invention converts binary inputs of fractional form into equivalent decimal outputs, e.g., series of digits, making the conversion especially useful with a digital differential analyzer computer which solves differential equations and performs other analog computations on fractional binary inputs.

DECRIPTION OF THE DRAWINGS

FIGS. 1a and 1b are circuit diagrams which together embody the present invention.

FIG. 2 is a timing diagram showing the operation of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 1a and 1b show the preferred embodiment of the present invention comprised of four major elements. The first, read pulse generator 2, is depicted as having two alternate modes: a manual mode with related circuitry 4 and an adjustable mode shown by circuitry 6. In both modes, read pulse generator 2 produces a pulse which designates the time at which a binary number is to be converted. More specifically, the output of pulse generator 2 is gated with a binary fraction word W at NOR gate arrangement 8, permitting binary numbers to be read in only when pulse generator 2 produces a read pulse. Pulses are generated in the manual mode by depressing switch 10; in the adjustable mode pulses are generated periodically and automatically by setting a ring counter 12 to a selected output.

Pulsed-in binary fraction words W enter the next major element, sign determination logic 14, which reads a sign bit SB associated with each binary fraction word W and concludes that the binary number to be converted is positive or negative. If the binary number represented by binary fraction word W is a negative fraction, the word is complemented in logic circuitry 16, the third major element, to produce an "equivalent" positive binary. If the binary number is positive no complementing takes place. The output of logic circuitry 16 in either case enters the final and most important element, multiplier stages 18.

Multiplier stages 18, in effect, multiply the incoming binary fraction word W by ten (1010 in binary), extract an integer portion representing the most significant decimal digit (MSD) therefrom, multiply the remaining fraction portion by ten (1010 in binary), extract the next MSD from the next integer portion and so on until the binary number is represented by decimal digits stored in holding registers 20 of multiplier stages 18. This general method of converting from binary-to-decimal by successively multiplying by ten (1010) is well-known in the art as evidenced by the discussion found in the aforementioned reference U.S. Pat. No. 3,257,547. However, the implementation of that method by the simplified, adaptable circuitry of the present invention, as shall now be more specifically described, represents an innovative departure from prior art binary-to-decimal converters.

Referring again to the first major element, pulse generator 2, manual mode circuitry 4 is shown connected via switch 10 to a voltage source V. (In the preferred embodiment negative logic metal oxide semiconductor/field effect transistor (MOS/FET) components are employed in pulse generator 2 and sign determination logic circuitry 14 because of their compactness and versatility. To be compatible with the MOS/FET negative logic, V = -14 volts.) In its normal, undepressed position, switch 10 connects an input of NOR gate 102 to voltage source V (which is hereafter referred to as 1 or high). Output from NOR gate 102 is then 0 (or low) corresponding to ground voltage; NOR gate 100 thus has two 0 (or low) inputs yielding a 1 (or high) output corresponding to V, or -14 volts. The outputs from NOR gates 100 and 102 are connected to the J and K leads, respectively, of a conventional J-K flip-flop 104. When switch 10 is in normal position, J = 1 and K = 0. When switch 10 is depressed, i.e., pushed-to-read (see arrow), -14 volts is fed to one input of NOR gate 100 and an input to NOR gate 102 is connected to ground through resistor R.sub.1. The output of NOR gate 100 becomes 0 and thus provides a second 0 input to NOR gate 102. The output from NOR gate 102 is 1; J is then 0 and K is 1. The Q and Q outputs of J-K flip-flop 104 feed into a second J-K flip-flop 106. As seen in FIG. 1a,the Q output of flip-flop 104 is connected to the J lead of flip-flop 106 and the Q output feeds the K lead of flip-flop 106. Flip-flops 104 and 106 are clocked at sign-bit (SB) time by clock CLK. In accordance with conventional J-K flip-flop logic, the Q output of flip-flop 106 will turn ON to the 1 state when the second sign-bit time is clocked after depressing switch 10. That is, at the first clock pulse from clock CLK flip-flop 104 changes state to turn ON Q of flip-flop 104; Q of flip-flop 106 remains at 0, however, until, at the second bit-time, a pulse is generated which causes flip-flop 106 to change state. Q of flip-flop 106 is connected as an input to NOR gate 108. When Q of flip-flop 106 is 0 during the first sign-bit time and Q of flip-flop 104 is also 0 (i.e., the 1 input at K of flip-flop 104 has set the Q output of flip-flop 104 to 0), it can be seen from FIG. 1a that NOR gate 108 has two 0 inputs. A pulse output of 1 on NOR gate 108 results. This pulse represents the read pulse generated by the manual mode circuitry 4 of read pulse generator 2.

A second input to NOR gate 108 comes from adjustable mode circuitry 6. The adjustable mode provides a conventional ring counter 12 which determines the value of the scale factor Y.DELTA.X of R Adder 110. Scale factor Y.DELTA.X is added to whatever input may be stored (as an initial value) in R Adder 110, the sum of which is shown as R.sub.OUT. The sum at R.sub.OUT is fed into R Register 112 which transfers the sum back into R Adder 110 at input R.sub.IN. From then on R.sub.IN is periodically incremented by scaling factor Y.DELTA.X and circulated through R Register 112 until R Adder 110 is "full". The next increment causes an overflow (or carry) at output .DELTA.Z which feeds the K input of J-K flip-flop 114. Depending on the position at which ring counter 112 is set, the contents of R Adder 110 can be incremented by an amount corresponding to from 64msec to 65 secs.

The J lead of flip-flop 114 is always high. Before overflow, J = 1 and K = 0; Q of flip-flop 114 is accordingly 1. The Q = 1 value is fed to NOR gate 108, causing a 0 (no pulse) output. When overflow at output .DELTA.Z changes K to a 1 state (J still being 1), Q of flip-flop 114 changes state to 0. Now at NOR gate 108 there are two 0 inputs which generate a read pulse output.

Lead 116 is provided to prevent simultaneous operation of the manual and adjustable modes and also to cause a pulse to be generated via NOR gate 108 when Q of flip-flop 104 and Q of flip-flop 106 are both 0.

The two 0 inputs to NOR gate 108 yield a pulse output which enters NOR gates 120 and 122. With a high input to each of these NOR gates 120 and 122, the outputs of both NOR gates 120 and 122 must be low ("0"). The 0 state of NOR gate 120 is then NORed with binary fraction word W in NOR gate 124. The 0 output of NOR gate 122 is then NORed with the output of NOR gate 124 in NOR gate 126 to effect a "reading in" of binary fraction word W. Binary fraction word W is then fed into a shift register 127. The contents of shift register 127 are circulated through NOR gates 122 and 126. It should, however, be noted that the contents are circulated only when the output of NOR gate 108 is in 0 state; that is, when no read pulse is being generated. Output from NOR gate 126 (of gating arrangement 8) enters a J-K flip-flop 128 which is clocked at sign-bit (SB) time.

If the sign-bit (generated at sign-bit time) is 1 indicating a negative binary number, the J input to flip-flop 128 is at 1 state and the K input to flip-flop 128 is made 0; Q.sub.B then is turned to the 1 used to drive the minus input of the .+-. Nixie. Conversely, if the sign bit is 0, J = 0 and K = 1 via NOR gate 130; Q.sub.B is then turned to the 1 state thereby corresponding to a positive binary number. The signals representing binary fraction word W and outputs Q.sub.B and Q.sub.B from sign-bit determination logic 14 are translated by conventional translator T into positive Transistor-Transistor Logic (TTL) which is notably faster and more adaptive to repetitive and cyclic operations. The translated signals then enter major element 16 (see FIG. 1b), the two's complement logic element. If Q.sub.B is in the 1 state, the binary fraction word W passes through NAND gate network 132 unaltered. However, if Q.sub.B is in the 1 state indicating a negative binary number, the two's complement of the binary fraction word W is generated in full adder 134. The complemented and passed through words W's are then treated identically as checked words + W's. The two's complement circuitry can, of course, be substituted by one's complement logic at the expense of introducing an error in the least significant bit which may be considerable where small numbers are being converted. The preferred embodiment performs the conversion in the conventional two's complement manner to achieve minimum error.